Referring to FIG. 1, a sense amplifier 100 of the prior art is used for determining the bit data of a core cell 102 that is typically part of a memory device. A current level (IR+Δi) through the core cell 102 varies depending on the bit data stored therein. A core bit voltage VCBIT is generated at a source of a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) 104 from the core cell 102.
The source of the first NMOSFET 104 and the core cell 102 are coupled to a negative input 108 of a first differential amplifier 106 that compares the core bit voltage VCBIT with a regulation reference voltage VREG—REF applied on a positive input 110 of the first differential amplifier 106. The output of the first differential amplifier 106 is coupled to a gate of the first NMOSFET 104 for stably maintaining the core bit voltage VCBIT.
A drain of the first NMOSFET 104 is coupled to a positive voltage supply VCC via a first resistor 112. A core output voltage VCORE is generated at the drain of the first NMOSFET 104 and is applied on a negative input of a comparator 120.
The sense amplifier 100 also includes a second NMOSFET 122 having a source coupled to a reference cell 124. A current level IR flows through the reference cell 124, and a reference bit voltage VRBIT is generated at the source of the second NMOSFET 122 from the reference cell 124.
The source of the second NMOSFET 122 and the reference cell 124 are coupled to a negative input 126 of a second differential amplifier 128 that compares the reference bit voltage VRBIT with the regulation reference voltage VREG—REF applied on a positive input 130 of the second differential amplifier 128. The output of the second differential amplifier 130 is coupled to a gate of the second NMOSFET 122 for stably maintaining the reference bit voltage VRBIT.
A drain of the second NMOSFET 122 is coupled to a positive voltage supply VCC via a second resistor 132. A reference output voltage VREF is generated at the drain of the second NMOSFET 122 and is applied on a positive input of the comparator 120.
The output of the comparator generates an output signal OUT that is a logical high state or a logical low state depending on the core output voltage VCORE compared to the reference output voltage VREF. Such a logical high or low state of the output signal OUT indicates the bit data stored within the core cell 102.
The current (IR+Δi) through the core cell has a current offset component Δi from the reference current IR through the reference cell 124 that varies depending on the bit data stored within the core cell 102. Such a variable current offset component Δi determines the core output voltage VCORE which in turn determines the logical state of the output signal OUT.
Unfortunately, the core output voltage VCORE in the sense amplifier 100 of the prior art has limited voltage swing because the core bit voltage VCBIT is relatively high and substantially close to the positive supply voltage VCC for proper operation of the core cell 102. For example, when the positive supply voltage VCC is about 1.8 Volts, the core bit voltage VCBIT is about 1.5 Volts for proper operation of the core cell 102. In addition, a voltage drop is generated across the first resistor 112. Thus for such example voltages, the core output voltage VCORE has a voltage swing of from about 0.2 Volts to about 0.3 Volts for maintaining the first NMOSFET 104 in saturation.
Such a low voltage swing of the core output voltage VCORE disadvantageously results in low sensitivity of the sense amplifier 100 in the prior art. Thus, sense amplifiers having higher voltage swing are desired for higher sensitivity.